An organic EL display device has been known as a thin-type, high picture quality, and low power consumption display device. In the organic EL display device, a plurality of pixel circuits including organic EL elements (also referred to as “Organic Light Emitting Diodes”) that are self-luminous type display elements driven by currents and driving transistors, are arranged in a matrix.
FIG. 13 is diagram illustrating a configuration of a pixel circuit 111 in the related art. As illustrated in FIG. 13, the pixel circuit 111 includes one organic EL element OLED, seven transistors M1 to M7, and a storage capacitor Cst. The transistors M1 to M7 all are P-channel type transistors.
The transistor M1 is a driving transistor for controlling a current to be supplied to the organic EL element OLED. The transistor M2 is a writing transistor for writing a voltage depending on a data signal (data voltage) into the pixel circuit 111. The transistor M3 is a compensation transistor for compensating variation in a threshold voltage of the driving transistor M1 which causes a luminance unevenness. The transistor M4 is a first initialization transistor for initializing a potential of a node N at which a gate terminal of the driving transistor M1 is connected to one terminal of the storage capacitor Cst described later, that is, a gate voltage Vg of the driving transistor M1. The transistor M5 is a power supply transistor for supplying a high level voltage ELVDD to the pixel circuit 111. The transistor M6 is a light emission control transistor for controlling a light emission period of the organic EL element OLED. The transistor M7 is a second initialization transistor for initializing an anode voltage of the organic EL element OLED.
The storage capacitor Cst is a capacitor including one terminal connected to the gate terminal of the driving transistor M1 via the node N and the other terminal connected to the high level power source line ELVDD, and holds, for one frame period, an electric charge equivalent to a voltage difference between the high level voltage ELVDD and a data voltage applied to the gate terminal of the driving transistor M1. In the pixel circuit 111, a data line capacitor Cdi that is a parasitic capacitance of a data line Di having been separated and the storage capacitor Cst are linked in a writing period. This allows an electric charge equivalent to the data voltage held in the data line capacitor Cdi to be distributed again into the data line capacitor Cdi and the storage capacitor Cst.
In the pixel circuit 111, before writing the data voltage into the node N, the first initialization transistor M4 provided between an initialization power source line Vini and the storage capacitor Cst is made to turn to an on state to decrease the potential of the node N to an initialization potential Vini. This allows the potential of the node N to be initialized so that the data voltage is written into the node N via the writing transistor M2, the driving transistor M1, and the compensation transistor M3 in the writing period in which a potential of a scanning line Sj is in a low level.
A low transconductance transistor is used for the above driving transistor M1 in order to facilitate control of a drive current for the display element OLED. In this case, even when it is attempted to write a data voltage of a potential the farthest from the initialization potential into the potential of the node N via the driving transistor M1 in the writing period, the writing cannot be made within the writing period, leading to charge shortage.
For example, the pixel circuit 111 including the P-channel type transistors writes a voltage on a lower level side as an initialization voltage and then allocates the voltage on the lower level side to a higher luminance side and a voltage on a higher level side to a lower luminance side. FIG. 14 is a timing chart illustrating pixel circuit actions of the pixel circuit 111 illustrated in FIG. 13. As illustrated in FIG. 14, when the scanning line Sj is changed from a high level to a low level at a time point t3, the potential of the node N cannot be charged to the data voltage for a short time, and thus the gate voltage Vg applied to the gate terminal of the driving transistor M1 cannot change from the initialization voltage to the voltage on the lower level side displaying a high luminance image for a short time. For this reason, the driving transistor M1 cannot supply a drive current displaying the high luminance image to the display element OLED.
FIG. 15 is a diagram illustrating a configuration of a pixel circuit 112 in the related art described in PLT 1. The pixel circuit 112 illustrated in FIG. 15 is further provided with a boost capacitor Cbs including a parallel-plate capacitor, in the pixel circuit 111 illustrated in FIG. 13. The boost capacitor Cbs includes one terminal connected to the scanning line Sj and the other terminal connected to the node N. The configuration is the same as the configuration illustrated in FIG. 13, and therefore, a description thereof is omitted. FIG. 16 is a timing chart illustrating actions of the pixel circuit 112 illustrated in FIG. 15. As illustrated in FIG. 16, in a case where the voltage applied to the scanning line Sj changes from the high level to the low level, the potential of the node N, that is, the gate voltage Vg of the driving transistor M1 is pushed down by the boost capacitor Cbs and decreased by a low level voltage applied to the scanning line Sj. In this way, the boost capacitor Cbs being provided allows the potential of the node N to be instantaneously pushed down, and therefore, when the scanning line Sj changes from the high level to the low level at the time point t3, the gate voltage Vg is instantaneously pushed down to a direction in which the drive current for the driving transistor M1 increases. This allows a source-gate voltage Vgs of the driving transistor M1 to increase so that the node N is charged with a data voltage Vdata supplied from the data line Di to improve a drive capability of the driving transistor M1. In association with this, the gate voltage Vg of the driving transistor M1 can transit from the initialization voltage to a voltage of the data voltage Vdata overlapped with a threshold voltage for a short time so that a threshold voltage Vth is compensated.
PTL 2 discloses a pixel circuit including a MOS capacitor provided between a gate of a driving transistor and a scanning line.